1. Field of the Invention
The present invention relates generally to Phase Locked Loop (PLL) Frequency Synthesizers. In particular, the present invention relates to a PLL Frequency Synthesizer incorporated into a radio communication apparatus in use for mobile communication systems such as a digital cellular telephone apparatus.
2. Background of the Invention
Recently, mobile communication systems have become widely spread. A typical example is a cellular telephone system. However, the radio frequency band used for such mobile communication has a limited number of channels available for assignment. It is therefore necessary to utilize the bandwidth efficiently. In order to make better use of the available bandwidth some efforts have been made, for example, making a channel space in the band width narrower.
In a radio communication apparatus for mobile communication, a Phase-Locked Loop (PLL) Frequency Synthesizer is often used as a local oscillator. A highly pure and stable signal is required as an output of the PLL Frequency Synthesizer and, in addition, a short Lock-Up Time (the time needed for stabilizing the frequency fo the output signal when it is set to change) is required.
A PLL Frequency Synthesizer according to the present invention is shown in FIG. 5. In this PLL Frequency Synthesizer, assuming that a channel space is fc, the referenced oscillating frequency fr of the output from a reference signal source 21 could be set as follows. EQU fr=fc (1)
Also, assuming that the divide ratio at the variable frequency divider 15 is N, the output frequency fo of a voltage controlled oscillator 14 could be set as follows. EQU fo=N X fr (2)
In the PLL Frequency Synthesizer in which the frequencies are preset as above, as the frequency band is made narrower for each of the radio channels within a certain frequency range, the frequency of the reference signal source 21 and the frequency of the output signal from a phase comparator 12 goes down. Therefore, low pass filter 13 requires a longer time constant to integrate an output of the phase comparator 12. This follows because it has to integrate a lower frequency signal. However, when the time constant is set longer, the Lock-Up Time characteristic of the PLL becomes worse, and therefore, it creates a problem.